1. Field of the Invention
This invention relates to a method and apparatus for separately driving a voltage in a plasma display panel, and more particularly to a separate voltage driving method and apparatus for a plasma display panel wherein abnormal brightness caused by a characteristic deviation of the panel is not only restrained, but also a damage of a switching device caused by an overcurrent is prevented. Also, the present invention is directed to a separate voltage driving method and apparatus for a plasma display panel wherein a sustaining voltage, a writing voltage and an erasing voltage are separated and adjusted in accordance with a characteristic deviation of the panel.
2. Description of the Related Art
Generally, a plasma display panel (PDP) radiates a fluorescent body by an ultraviolet with a wavelength of 147 nm generated during a discharge of He+Xe or Ne+Xe gas to thereby display a picture including characters and graphics. Such a PDP is easy to be made into a thin film and large-dimension type. Moreover, the PDP provides a very improved picture quality owing to a recent technical development. The PDP is largely classified into a direct current (DC) driving system and an alternating current (AC) driving system.
Since the AC-type PDP has an advantage of a low voltage driving and a long life in comparison to the DC-type PDP, it will be highlighted as the future display device. The AC-type PDP allows an alternating voltage signal to be applied between electrodes having dielectric layer therebetween to generate a discharge every half-period of the signal, thereby displaying a picture. Since such an AC-type PDP uses a dielectric material that allows a wall charge to be accumulated on the surface thereof upon discharge, it exerts a memory effect.
Referring to FIG. 1 and FIG. 2, the AC-type PDP includes a front substrate 1 provided with a sustaining electrode pair 10, and a rear substrate 2 provided with address electrodes 4. The front substrate 1 and the rear substrate 2 are spaced in parallel to each other with having barrier ribs 3 therebetween. A mixture gas, such as Ne--Xe or He--Xe, etc., is injected into a discharge space defined by the front substrate 1, the rear substrate 2 and the barrier ribs 3. These sustaining electrodes 10 make a pair by two within a single of plasma discharge channel. Any one electrode of the sustaining electrode pair 10 is used as a scanning/sustaining electrode that responds to a scanning pulse applied in an address interval to cause an opposite discharge along with the address electrode 4 while responding to a sustaining pulse applied in a sustaining interval to cause a surface discharge with the adjacent sustaining electrodes 10. Also, the sustaining electrode 10 adjacent to the sustaining electrode 10 used as the scanning/sustaining electrode is used as a common sustaining electrode to which a sustaining pulse is applied commonly. On the front substrate 1 provided with the sustaining electrodes 10, a dielectric layer 8 and a protective layer 9 are disposed. The dielectric layer 8 is responsible for limiting a plasma discharge current as well as accumulating a wall charge during the discharge. The protective film 9 prevents a damage of the dielectric layer 8 caused by the sputtering generated during the plasma discharge and improves the emission efficiency of secondary electrons. This protective film 9 is usually made from MgO. The rear substrate 2 is provided with a dielectric thick film 6 covering the address electrodes 4. The barrier ribs 3 for dividing the discharge space are extended perpendicularly at the rear substrate 2. On the surfaces of the rear substrate 2 and the barrier ribs 3, a fluorescent material 5 excited by a vacuum ultraviolet lay to generate a visible light is provided.
As shown in FIG. 3, the PDP 21 has mxn discharge pixel cells 11 arranged in a matrix pattern. At each of the discharge pixel cells 11, scanning/sustaining electrode lines Y1 to Ym, hereinafter referred to as "Y electrode lines", and common sustaining electrode lines Z1 to Zm, hereinafter referred to as "Z electrode lines", and address electrode lines X1 to Xn, hereinafter referred to as "X electrode lines" are crossed with respect to each other. The Y electrode lines Y1 to Ym and the Z electrode lines Z1 to Zm consist of the sustaining electrode 10 making a pair. The X electrode lines X1 to Xn consist of the address electrode 4.
FIG. 3 is a schematic view of a PDP driver shown in FIG. 1. In FIG. 3, the PDP driver includes a scanning/sustaining driver 22 for driving the Y electrode lines Y1 to Ym, a common sustaining driver 24 for driving the Z electrode lines Z1 to Zm, and first and second address drivers 26A and 26B for driving the X electrode lines X1 to Xn. The scanning/sustaining driver 22 is connected to the Y electrode lines Y1 to Ym to thereby select a scanning line and cause a sustaining discharge at the selected scanning line. The common sustaining driver 24 is commonly connected to the Z electrode lines Z1 to Zm to apply sustaining pulses with same waveform to all the Z electrode lines Z1 to Zm, thereby causing the sustaining discharge. The first address driver 26A supplies odd-numbered X electrode lines X1, X3, . . . , Xn-3, Xn-1 with a video data, whereas the second address driver 26B supplies even-numbered X electrode lines X2, X4, . . . , Xn-2, Xn with a video data.
In such an AC-type PDP, one frame consists of a number of sub-fields so as to realize gray levels by a combination of the sub-fields. For instance, when it is intended to realize 256 gray levels, one frame interval is time-divided into 8 sub-fields. Further, each of the 8 sub-fields is again divided into a reset interval, an address interval and a sustaining interval. The entire field is initialized in the reset interval. The cells on which a data is to be displayed are selected by a writing discharge in the address interval. The selected cells sustain the discharge in the sustaining interval. The sustaining interval is lengthened by an interval corresponding to 2.sup.n depending on a weighting value of each sub-field. In other words, the sustaining interval involved in each of first to eighth sub-fields increases at a ratio of 2.sup.0, 2.sup.1, 2.sup.3, 2.sup.4, 2.sup.5, 2.sup.6 and 2.sup.7. To this end, the number of sustaining pulses generated in the sustaining interval also increases into 2.sup.0, 2.sup.1, 2.sup.3, 2.sup.4, 2.sup.5, 2.sup.6 and 2.sup.7. depending on the sub-fields. The brightness and the chrominance of a displayed image are determined in accordance with a combination of the sub-fields.
FIG. 4 is a detailed circuit diagram of the scanning/sustaining driver shown in FIG. 3. In FIG. 4, the scanning/sustaining driver 22 includes a voltage input/output stage 22a, a writing/erasure scanning voltage generator 22b, a sustaining voltage generator 22c and a voltage recovery stage 22d so as to apply a driving pulse to any one of m Y electrode lines Y1 to Ym. The voltage input/output stage 22a consists of first and second switching devices Q1 and Q2 connected, in series, to each other, and diodes D1 and D2 connected, in parallel, to the first and second switching devices Q1 and Q2, respectively. The first and second switching devices Q1 and Q2 are selectively switched in response to a control signal applied from a controller (not shown) . Thus, the first and second switching devices Q1 and Q2 applies a writing/erasure scanning pulse voltage Vp and a sustaining voltage VH to a pixel cell 11 of the panel 20. The sustaining voltage generator 22c consists of third and fourth switching devices Q3 and Q4 connected, in series, between a sustaining voltage (VH) supply terminal and a ground terminal GND, and fifth and sixth switching devices Q5 and Q6 and diodes D3 and D4 connected to a middle voltage VM having a half level of the sustaining voltage VH to make a closed loop. The third and fourth switching devices Q3 and Q4 are selectively switched in response to a control signal applied from the controller. If the switching device Q3 is turned on, then the sustaining voltage VH is applied, via the diode D2 included in the voltage input/output stage 22a, to the panel 20. On the other hand, if the switching device Q4 is turned on, then a voltage having been charged in the panel 20 is coupled with the ground terminal GND. The fifth and sixth switching devices Q5 and Q6 respond to a control signal applied from the controller to apply the middle voltage VM to the panel 20. The writing/erasure scanning voltage generator 22b a writing/erasure scanning voltage VP into the capacitor C1 when the fourth switch Q4 of the sustaining voltage generator 22c has been turned on. The writing/erasure scanning voltage generator 22b applies a voltage charged in the capacitor C1 to the panel 20 when the third switch Q3 of the sustaining voltage generator 22c. The voltage recovery stage 22d consists of capacitors C2 and C3 connected to a ground terminal GND, seventh and eighth switching devices Q7 and Q8 and diodes D5 and D6 connected to a second capacitor C2 to make a closed loop, and ninth and tenth switching devices Q9 and Q10 and diodes D7 and D8 to make a closed loop. If the eighth and tenth switching devices Q8 and Q10 are turned on, then an invalid power at the panel 20 is recovered. The recovered invalid power is accumulated at a different voltage level in the capacitors C2 and C3. If the seventh and ninth switching devices Q7 and Q9 are turned on, then the voltage accumulated in the capacitors C2 and C3 is applied to the panel 20. The voltage input/output stage 22a, the writing/erasure scanning voltage generator 22b, the sustaining voltage generator 22c and the voltage recovery stage 22d installed at the common sustaining driver 24 are symmetrically arranged around the panel 20.
An operation process of the scanning/sustaining driver 22 will be described in detail with reference to FIG. 5, in which (a) shows a waveform applied to the X electrode lines; (b) shows a waveform applied to the Y electrode lines; (c) shows a waveform applied to the Z electrode lines; and (d) to (k) represent switching timings for producing waveforms of (b) and (c). First, in the sustaining discharge interval of the previous sub-field, a high pulse having a certain period as shown in (f) and (g) of FIG. 5 is applied from the controller to gate terminals G5 and G6 of the fifth and sixth switching devices Q5 and Q6. If the fifth and sixth switching devices Q5 and Q6 are turned on, then a middle voltage VM is applied, via the fifth switching device Q5, the third diode D3 and the second diode D2, to the panel 20. In other words, the Y electrode line Y is coupled with a middle voltage VM as shown in (b) of FIG. 5. The middle voltage VM applied from the common sustaining driver 24 to the Z electrode line Z is applied to the second switching device Q2, the fourth diode D4 and the sixth switching device Q6. In other words, if the sixth switching device Q6 is turned on, then a level of a voltage applied to the Z electrode line Z remains at the middle voltage VM accurately as shown in (c) of FIG. 5. After the middle voltage VM was applied to the Y electrode line Y and the Z electrode line Z for a desired time, a high pulse with a desired period T5 as shown in (k) of FIG. 5 is applied to the gate terminal G10 of the tenth switching device Q10. The tenth switching device Q10 is turned on in response to this high pulse. If the tenth switching device Q10 is turned on, then an invalid power is recovered from a panel capacitor formed equivalently by the Z electrode line Z and the Y electrode line Y. In other words, electric charges of the middle voltage VM accumulated in the panel capacitor for a desired period T5 when the tenth switching device Q10 is turned on, are accumulated, via the second switching device Q2, a reactor L1, an eighth diode D8 and the tenth switching device Q10, into the capacitor C3. At this time, a half level of the middle voltage VM, that is, a voltage of Vm/2 is accumulated in the capacitor C3. The voltage accumulated in the capacitor C3 is discharged in the sustaining interval of the next middle voltage VM. After a voltage of 2/VM was accumulated in the capacitor C3, the fifth and sixth switching devices Q5 and Q6 are turned off and, at the same time, a high pulse with a desired period T1 as shown in (e) of FIG. 5 is applied to the gate terminal G4 of the fourth switching device Q4. The fourth switching device Q4 is turned on in response to this high pulse. If the fourth switching device Q4 is turned on, then the Y electrode line Y is connected to the ground terminal GND. Thus, a sustaining pulse VP less than the middle voltage, that is, with a negative voltage and a writing pulse WP with a writing potential are obtained at the Y electrode line Y. On the other hand, a writing or erasure scanning voltage VP is accumulated in the capacitor C1 of the writing/erasure scanning voltage generator 22b when the fourth switching device Q4 is turned on. The VP is used as a voltage of the writing pulse WP and the erasure scanning pulse ESP.
A process of applying the writing pulse WP to the Y electrode line Y will be described including the scanning/sustaining driver 24 below. When the fourth switching device Q4 is turned on, the writing voltage VP accumulated in the first capacitor C1 of the scanning/sustaining driver 24 is added to the middle voltage VM and then is suddenly bypassed via the second switching device Q2 and the fourth switching device Q4. The voltage VP of the writing pulse WP plus the sustaining voltage VH less than the middle voltage, that is, with a negative voltage as shown in (b) of FIG. 5 is applied to the Y electrode line Y for a desired period T1. The voltage VP of the writing pulse WP is added to a voltage as shown in (c) of FIG. 5, which is synchronized with the sustaining pulse less than the middle voltage VM applied to the Y electrode line and the writing pulse WP and has a phase contrary to each other, that is, a positive of sustaining voltage VH, to be applied to the Z electrode line Z. When the fifth and sixth switching devices Q5 and Q6 are turned off, the third switching device Q3 and the first switching device Q1 are turned on for a desired period T1. Thus, the sustaining voltage VH is added to the writing voltage WP accumulated in the first capacitor C1 to be applied, via the first switching device Q1, to the Z electrode line Z.
As described above, if the synchronized writing pulse WP having a contrary phase as shown in (b) and (c) of FIG. 5 is applied to the Y electrode lines Y1 to Ym and the Z electrode lines Z1 to Zm, then a discharge is initiated by a voltage difference 2WP of two writing pulses WP. The pixel cells initiating the discharge in this manner make a writing discharge to be radiated. At this time, a positive(+) polarity of wall charge is formed at the Y electrode line Y while a negative(-) polarity of wall charge is formed at the Z electrode line Z.
Since such a writing discharge is influenced by the previous field state of the discharge cell, however, it becomes unstable. Accordingly, in order to make a stable discharge of all the cells, a sustaining pulse SP having a phase contrary to each other and synchronized as shown in (b) and (c) of FIG. 5 is applied.
A process of producing such a sustaining pulse SP will be described below. First, a high pulse having a desired period T4 as shown in (j) of FIG. 5 is applied to a gate terminal G9 of the ninth switching device Q9 just before the fourth switching device Q4 is turned off. The ninth switching device Q9 is turned on in response to this high pulse. If the ninth switching device Q9 is turned on, then a voltage of VM/2 having been accumulated in the third capacitor C3 is discharged. The discharged voltage is applied, via the ninth switching device Q9, the seventh diode D7, the reactor L1 and the second diode D2, to the Y electrode line Y. In other words, the Y electrode line Y maintains a sustaining voltage VH larger than the ground voltage GND as shown in (b) of FIG. 5. When the Y electrode line Y remains at the sustaining voltage VH larger than the ground voltage GND, the fourth switching device Q4 is turned off. At this time, a high pulse having a desired period T2 as shown in (f) of FIG. 5 is applied to a gate terminal G5 of the fifth switching device Q5. The fifth switching device Q5 is turned on in response to this high pulse. If the fifth switching device Q5 is turned on, then the sustaining voltage VH larger than the ground voltage GND rises during a desired period T2 to maintain the middle voltage VM. This middle voltage VM is applied, via the fifth switching device Q5, the third diode D3 and the second diode D2, to the Y electrode line Y. When the middle voltage VM is applied to the Y electrode line Y, a high pulse having a desired period T3 as shown in (h) of FIG. 5 is applied to a gate terminal G7 of the seventh switching device Q7. The seventh switching device Q7 is turned on in response to this high pulse. If the seventh switching device Q7 is turned on, then a voltage larger than the middle voltage VM accumulated in the second capacitor C2, that is, a voltage of (VH+VM)/2 is discharged. This discharge voltage is applied, via the seventh switching device Q7, the fifth diode D5, the reactor L1 and the second switching device Q2, to the Y electrode line Y. As a result, as shown in (b) of FIG. 5, a voltage of (VH+VM)/2 is applied to the Y electrode line Y for a desired period T3.
After the voltage of (VH+VM)/2 was applied to the Y electrode line Y, the fifth switching device Q5 is turned off. When the fifth switching device Q5 is turned off, a high pulse having a desired period T6 as shown in (d) of FIG. 5 is applied to a gate terminal of the third switching device Q3. The third switching device Q3 is turned on in response to this high pulse. If the third switching device Q3 is turned on, then the sustaining voltage VH is applied, via the third switching device Q3 and the second switching device Q2, to the Y electrode line Y. Thus, a sustaining pulse having a higher potential than the middle voltage VM as shown in (b) of FIG. 5, that is, a positive sustaining pulse SP is applied to the Y electrode line Y during a desired period T6. On the other hand, a sustaining pulse SP having a phase contrary to the sustaining pulse SP applied to the Y electrode line Y as shown in (c) of FIG. 5 is applied to the Z electrode line Z. The sustaining pulse SP applied to the Z electrode line Z is bypassed via the second switching device Q2 and the fourth switching device Q4. Accordingly, a negative sustaining pulse having a ground voltage GND is applied to the Z electrode line Z.
If a synchronized sustaining pulse SP having a contrary phase is applied to the Y and Z electrode lines Y and Z is applied, then an electric field forming wall charges at the panel 20 is superposed with an applying electric field. In other words, a sustaining discharge is caused by a sustaining voltage difference 2SP between two electrodes. Accordingly, a writing discharge becomes stable and wall charges are formed at a constant level. a formation position of the wall charges is changed to form a negative(-) polarity of wall charges at the Y electrode lines and to form a positive(+) polarity of wall charges at the Z electrode lines. A high pulse as shown in (i) of FIG. 5 is applied to a gate terminal G8 of the eighth switching device Q8 upon the lapse of the desired period T6, that is, prior to the shutting-off of the third switching device Q3. The eighth switching device Q8 is turned on in response to this high pulse. If the eighth switching device Q8 is turned on, then the sustaining voltage VH is accumulated, via the reactor L1 and the sixth diode D6, into the second capacitor C2 at a value of (VH+VM)/2. When the voltage is accumulated, the third switching device Q3 is turned off. When the third switching device Q3 is turned off, high pulses having desired periods T8 and T9 as shown in (f) and (g) of FIG. 5 are applied to gate terminals G5 and G6 of the fifth and sixth switching devices Q5 and Q6, respectively. The fifth and sixth switching devices Q5 and Q6 are turned on in response to these high pulses. If the fifth and sixth switching devices Q5 and Q6 are turned on, then the Y electrode line Y remains at the middle voltage VM as shown in (b) of FIG. 5. At this time, a positive address pulse as shown in (a) of FIG. 5 is applied from the address driver 26 to the X electrode line in the cells to be turned off. An erasure pulse ESP as shown in (b) of FIG. 5 is synchronized with the address pulse to be applied to the Y electrode line Y during the desired periods T8 and T9. At the cells coupled with the erasure pulse ESP and the address pulse, a minute discharge, that is, an erasing discharge is generated to terminate an emitting discharge. More specifically, a certain cell arranged in a matrix pattern can be selected by the erasure pulse ESP applied to the Y electrode line Y and the address pulse applied to the X electrode line X. At the discharge cell coupled with the erasure pulse ESP and the address pulse, an erasing discharge is generated. In other words, a wall voltage remains at a ground level to terminate an emitting discharge. The Z electrode line Z remains at the middle voltage VM in such an address interval. In other words, a discharge is not generated between the Z electrode line Z coupled with the middle voltage VM and the Y electrode line Y coupled with the erasure pulse ESP.
A process of producing the erasure pulse ESP applied to the Y electrode line Y will be described in detail below. First, high pulses having desired periods T8 and T9 as shown in (f) and (g) of FIG. 5 are applied to the fifth and sixth switching devices Q5 and Q6, respectively. The fifth and sixth switching devices Q5 and Q6 are turned on in response to these high pulses. The first and second switching devices Q1 and Q2 are alternately turned on at a state of turning on the fifth and sixth switching devices Q5 and Q6. Thereafter, the first and second switching devices Q1 and Q2 are alternately turned on with having timing synchronized with the address pulse. If the second switching device Q2 is turned on, then the Y electrode line Y remains at the middle voltage VM. If the first switching device Q1 is turned on, then the middle voltage VM applied to the Y electrode line Y is superposed with the voltage VP of the erasure pulse ESP accumulated in the first capacitor C1 to be applied to the Y electrode line Y. At this time, the Z electrode line Z remains at the middle voltage VM for the desired periods T8 and T9. On the other hand, the address pulse is synchronized with the erasure pulse ESP and, thus, is not applied to the discharge cell to be turned on. In other words, an erasing discharge is not generated to maintain an emitting discharge in the sustaining interval (not shown). During an erasure period (not shown), an address pulse is applied to the X electrode line X and an erasure pulse synchronized with this address pulse is applied to the Y electrode lines Y1 to Ym to thereby terminate an emitting discharge of the entire discharge cells.
The conventional PDP applies a high level of sustaining pulse, via the switching devices included in the voltage input/output stage, to the panel. At this time, a heat may be generated by a voltage drop according to resistance values of the switching devices included in the voltage input/output stage to damage the switching devices. Large power consumption is caused by resistance values of the switching devices itself. Also, an output voltage of the panel is lowered at the Y electrode line coupled with a large sustaining pulse current. Thus, at the Y electrode line coupled with a large sustaining pulse current, an abnormal brightness allowing a portion corresponding to the electrode area to become dark is generated. Furthermore, the conventional PDP produces the erasing pulse and the writing pulse using a single voltage VP. At this time, to make a voltage level of the writing pulse more than a desired level provides an easy writing. However, the conventional PDP has a problem in that, if an erasing pulse having a voltage more than a desired voltage level is applied, then an erasure is made at a time when an erasure must not be made.